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Abstract
The thesis aims at finding a global methodology for the test of boards having partially BS components. Which represent the more difficult case of testing. this thesis include five chapter In chapter 1: Describes the basic test concepts and Defines the Boundary Scan test in details.
In chapter 2: Defines the protocol used in this test and Elabors model for controlling the test protocol.
In chapter 3: Defines JTAGer software program tool based on BS test application.
In chapter 4: Unifies a global methodology using the above mentioned model and introduces an experimental setup to perform and validate the proposed methodology.
In chapter 5: Introduces a new idea for new test kit equipped with the author used for testing array or matrix of chips up to 24 I/O.
A methodology which unifies the test of components and their interconnects. It is based on a scheduling approach to simultaneously test both BS components and non-BS logic clusters, as well as interconnects. Short and open faults are also detected and addressed