الفهرس 
Thesis ScopeOnly 14 pages are availabe for public view
 |  | from | 123 |  |  |
| | | from | 123 | | |
Abstract
Filtering signals in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively [1].
Modern field programmable gate arrays (FPGAs) include the resources needed to design efficient filtering structures. Furthermore, some manufacturers now include complete microprocessors within the FPGA fabric. This mix of hardware and embedded software on a single chip is ideal for fast filter structures with arithmetic intensive adaptive algorithms.
This thesis aims to combine efficient filter structures with optimized code to create a system-on-chip (SOC) solution for various adaptive filtering problems. Several different adaptive algorithms have been coded in VHDL as well as in MATLAB and C. The designs are evaluated in terms of speed, hardware resources, and power consumption.
System identification is one of the most interesting applications for adaptive filters, especially for the Least Mean Square algorithm, due to its strength and calculus simplicity. Based on the error signal, the filter’s coefficients are updated and after certain conversion time filter’s coefficients becomes almost exactly the unknown system’ coefficients .System identification was mapped into a hardware description language, VHDL. The hardware was synthesized using FPGA (Xilinx Spartan3 3s200ft256 kit) with 50 MHz clock. Testing and verification procedures are described in details.