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Abstract This dissertation demonstrates the design of a Fractional-N PhaseLocked Loop. It begins with an introduction to Phase-Locked Loops. Different types and architectures of Phase-Locked Loops are discussed. Next, it presents different techniques used in Noise Cancellation and Charge Pump Linearization. A new technique that addresses both Charge Pump Non-Linearity and Delta Sigma Noise Cancellation is then presented. Afterwards, a Phase-Locked Loop System is designed employing the proposed architecture. FinaJly, different circuit blocks of the Phase- Locked Loop are designed and simulated. |