الفهرس 
Modulated Frequency SynthesizersOnly 14 pages are availabe for public view
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Abstract
Smart environments represent the next evolutionary development step in the automation of
buildings, utilities, industrial locations, homes, shipboards, and transportation systems. Like
any sentient organism, the smart environment relies first and foremost on sensory data from
the real world. Sensory data comes from multiple sensors in distributed locations. Wireless
connectivity of a vast number of industrial and home applications has modest transmission data
requirements, but demands reliable and secure communication using simple low-cost and low-
power radio systems. The need for cost and power effective radio solutions for this vast number
of fairly simple applications was addressed by a standardized technology. The IEEE 802.15.4
standard and ZigBee wireless technology are designed to satisfy the market’s need for a low-cost,
standard-based, and flexible wireless network technology, which offer low power consumption,
reliability, and security for control and monitoring applications with low to moderate data rates.
This thesis presents a 2.4GHz two-point modulated sigma-delta (1:.6.) Fractional-N frequency synthesizer designed to meet the IEEE 802.15.4 specifications with the lowest achievable power
consumption. The two-point modulation technique splits the modulated signal into two portions.
One portion is sent to the voltage-controlled oscillator (VCO) input and the other to the
E.6. modulator. This technique results ill constant modulation sensitivity regardless of the loop
bandwidth. However, timing and gain mismatches between two modulation paths are challenging
issues that can result in signal distortion.
The frequency synthesizer is designed to achieve -100dBc/Hz at IMHz offset and a maximum
of 20~c settling time with loop bandwidth equals to 290kHz. The design makes use of the
relaxed specification of the IEEE 802.15.4 standard to ach.ieve a very low power consumption
figure. The gain mismatch between the two paths is analyzed and the VCO gain variation effect
on the total transmitted error vector magnitude (EVM) is quantified. This work proposes a novel
open-loop calibration technique which is done for each channel after fabrication and the outputs
are saved to a look-up table. This ca1.ibration technique makes use of the fast settling behavior
of the phase locked loop (PLL) and it adjusts the gain mismatch to be below 10% within 50lJSec.
All circuits are designed using CMOS 0.13J..Ul11P6M, CMOS RF process. In order to decrease
the total power consumption, all circuits arc supplied with 1V supply. This work achieves total
EVM better than 15% using a novel VCO gain calibration technique. Finally, optimizing the system specifications for the sake oflower power consumption results in consuming about 3.25mW,
outperforming the state-of-the-art IEEE 802.15.4 transmitters and even frequency synthesizers.