الفهرس 
History of Floating Point Units on FPGAsOnly 14 pages are availabe for public view
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Abstract
Nowadays, every CPU has one or more Floating Point Units (FPUs) integrated
within it, FPUs are commonly used in math extensive applications, such as digital
signal processing. Consequently, FPUs find place In engineering, medical and
military fields as well as in other fields requiring audio, image or video manipulation.
The main operations of a conventional FPU are multiplication and
addition/subtraction accounting for 94% of the operations of a conventional FPU [1).
With the advancement in FPGAs, high performance FPGAs are now built with
millions of gates along with sophisticated features. Accordingly FPGAs are becoming
more suitable for implementation of high performance FPUs especially when short
time to market, low development cost and flexibility are required.
The objective of this thesis is to design and implement high speed generic FP
Multiplier and Adder/Subtracter Unit that competed with existing designs.
A novel multiplication algorithm is proposed and used in the implementation
of a FP Multiplier Unit whilst a FP Adder/Subtracter Unit is implemented using the
standard Leading One Detector (LOD) algorithm. Tbe novel multiplication algorithm
is referred to as ”Block Multiplication” and is used to optimize the large
multiplication operation in the FP MUltiplier by dividing it into several smaller
multiplications performed in parallel. In order to achieve high operating speeds both
the FP Multiplier and Adder/Subtracter Units are deeply pipelined which also lead to maximum throughput.
The FP Multiplier Unit using the novel Block Multiplication algorithm and the
FP Adder Unit using the LOD algorithm were both completely described using
VHDL code to allow their implementation to any FPGA platform. In our research,both units were implemented on Virtex2Pro, Virtex4 and Virtex5 FPGAs and were
able to operate at speeds higher than 320 MHz on Virtex2pro whilst occupying
around 20% of the FPGA and at speeds higher than 400 MHz on Virtex4 and VirtexS
FPGA whilst occupying around 3% of the FPGA. Post route simulation of both units
was performed to verify design operation post implementation (routing) and power
consumption was calculated post routing for most accurate analysis.