الفهرس 
Chapter 1: IntroductionOnly 14 pages are availabe for public view
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Abstract
Architecture-Level simulator is developed to determine the ability of different NoC communication schemes to mitigate the impact of process variation. The proposed simulator supports both synchronous and asynchronous NoCs. When compared with circuit implementation, the proposed simulator shows similarities in behavior when moving from a technology node to another. Clock skew represents 27% and 32% of synchronous NoC total delay variation for 45nm and 32nm technologies, respectively. Using real traffic and, unlike Circuit-Level analysis, Architecture-Level analysis shows a considerable throughput reduction in case of synchronous NoC under PV conditions. Throughput degradation increases rapidly with advance in technology for synchronous NoC. For different NoC sizes with different traffic workloads, throughput reduction for synchronous design is more than double the reduction of asynchronous design which unfavor the synchronous network from throughput points of view. Asynchronous scheme is preferable as technology scales.
A congestion aware, fault tolerant and process variation aware adaptive routing algorithm (CFPA) is introduced for congested and faulty asynchronous NoCs. The queuing delay is used as an indication for congestion. The proposed routing tables store multiple paths to every destination via all polar directions, which makes CFPA a fault tolerant algorithm in case of path failures.
On average, CFPA enhances the NoC throughput by 60% compared to the recently proposed routing algorithms. With CFPA, the impact of faults on NoC throughput is alleviated by 48%. In addition, the average delay of messages routed using CFPA is shorter than that of other algorithms by (26~75) % under process variation conditions.