الفهرس 
INTRODUCTIONOnly 14 pages are availabe for public view
 |  | from | 115 |  |  |
| | | from | 115 | | |
Abstract
High-speed serial data link interfaces have improved the performance of the modern commercial electronic applications such as memory and display applications. Many serial data link topologies such as SerDes (Serializer/Deserializer) architecture, time-based architecture and pulse-amplitude modulation (PAM) architecture have been proposed as discussed in the literature review. The main challenges in designing these different topologies are increasing the data rate of the transmitted data signals, minimizing the effects of the imperfections of the commercial transmission channel on the integrity of the transmitted signals and ensuring a correct recovery of the transmitted data bits. Increasing the number of the transmitted data bits using the PAM approach complicates the design of the receiver circuit to achieve an acceptable BER (bit error rate). The main contribution of this thesis is designing a time-based serial data link architecture that involves dual modulation Pulse Position Modulation approach (DMPPM). In the proposed approach, both the rising and falling edges of the input clock signal are modulated independently. Using the proposed approach allows increasing the total number of transmitted bits without significantly affecting the modulated signal bandwidth. A 6-bit 4.8 Gb/s DMPPM link design example has been designed and simulated based on the proposed approach in 130nm CMOS technology. A 800MHz has been used as an input clock signal. The simulation results and a comparison between the proposed link and other serial links are presented. The power consumption of the transmitter and the receiver circuits are less than 100mW. The proposed design substantiates an improvement in the bandwidth and simplifies the circuit complexity, in addition, increasing the number of transmitted bits as will discuss in the next chapters.