الفهرس 
Related WorkOnly 14 pages are availabe for public view
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Abstract
Network on Chip (NoC) has risen as an interconnection solution for the advanced digital systems, particularly for System on Chip (SoC), because of the huge number of Intellectual Properties (IPs) in the system that need to impart. Different routers and systems have been presented; subsequently the need to make a reusable verification environment to test both single routers and networks. In our thesis, we additionally propose a generic verification environment for NoC using the Universal Verification Methodology (UVM) that tests and verifies both routers and networks in an effortlessly modifiable way to fit different routers and networks.
As opposed to past projections using traditional bus-based interconnections, the utilization of NoC as an interconnection platform has turned out to be more promising to solve complex on-chip communication issues because of what it offers from reusability, scalability and efficiency. Besides, giving a reasonable test base to investigate and verify functionality of any IP core is a necessary stage. To expand; UVM is presented as a reusable and standardized methodology for verifying integrated circuit designs. In our thesis, we begun by introducing an architecture of a complete UVM environment to test generic routers through different test cases giving diverse scenarios to be applied. We likewise intend to establish a base on which other researchers can build to continue towards discovering better solutions.
Error injection has become critically important for testing the reliability of a newly designed hardware system. Evaluating how a Design Under Test (DUT) reacts to different error injection methodologies is very essential for verification engineers to design dependable UVM scoreboards for error-detection purposes. The first main contribution of our thesis is to decide on the feasibility and compatibility of error injection techniques when used with NoC platforms for simulation and hardware emulation environments. We target a UVM-based error injection and detection environment with reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two examples of NoC components: a base router and Daniel router. Base router is a simple case study to prove proposed schemes, whereas Danial router is a complex re-configurable open-source case study. Daniel router provides the ability of changing router architecture with some parameters and applied algorithms. The second main contribution of the thesis is to integrate a full UVM environment with various approaches. Approaches include error injection and detection using reusable and generic UVM environment and components for NoC. Network response is inspected according to error type and methodology.
Finally, the proposed UVM environment is implemented to test and verify an N × N 2-D or 3-D network composed of base routers or Daniel routers. It calculates the average latency in cycles and the average throughput in packets per cycle per processing element. Both are resolved along a range of injection rates measured in packets per cycle per processing element. The acquired results are compatible with the router efficiency.