الفهرس 
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Abstract
M
any of System on Chips (SoCs) applications, like portable devices and handheld applications, that either powered from batteries or using energy harvesting techniques, require advanced power management techniques such that it can perform its function efficiently with high performance while consuming low power. The Low Dropout Voltage Regulator (LDO) is one of the most important blocks used in power management systems, as many LDOs can be used in one system. Thus, a fully integrated capless-LDO that can respond fast enough to load/supply variations while consuming low power is highly required in electronics industry.
In this work, a new architecture for capless-LDO is presented that can be used in SoCs applications. The proposed architecture integrating two different types of pass transistors to work together in a single LDO while using a single error amplifier. The system can be viewed as two parallel LDOs working with one error amplifier. The usage of this two power transistors helped in relaxing the stability requirements of the system using a 600 fF compensation capacitor. In addition to relaxing the stability requirements, it can also supply wide range of load current. By making use of the low output impedance of the NMOS pass transistor and the driving current capability and the gain of the PMOS pass transistor, the capless-LDO can provide a fast transient response to sudden variations either in load current or in the supply voltage while consuming only 20.5 µA at low load current (95 µA at high load current). Also, the proposed capless-LDO can provide good line/load regulation.
The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0-50 pF with phase margin that increases from 43º at low load (10 µA) to 74º at high load (100 mA) and power supply rejection ratio (PSRR) less than -20dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm2. Post layout simulations show better performance compared with other reported technique.