الفهرس 
CHAPTER : ONE INTRODUCTIONOnly 14 pages are availabe for public view
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Abstract
Power Gating (PG) is of great importance in the digital circuit, which can reduce leakage power by switching off circuit module when not used in circuit operation. A robust power gating design using Graphene Nano-Ribbon Field-Effect Transistors (GNRFET) is proposed using 16nm technology.
This thesis focuses on designing and simulating different power gating structure, the Power Gating structure is composed of GNRFET as a footer Sleep Transistor and Silicon-CMOS logic Networks. The proposed structure handles the main drawbacks of the traditional PG design from point of view the propagation delay and wake up time in low–voltage regions. GNRFET/MOSFET Conjunction (GMC) is employed to build various structures of PG; GMCPG-SS and GMCPG-NS.
In addition to exploiting it to build two multi-mode PG structures. Circuit analysis for CMOS power gated logic modules (ISCAS85 benchmark) of 16nm technology is used to evaluate the performance of the proposed GNR power switch and this performance is compared to that of the traditional MOS. Leakage power, wake-up time and power delay product are used as performance circuit parameters for the evaluation. GMCPG-SS performance results reveal reduction in leakage power, delay time, and wake-up time, on average up to 88%, 44%, and 24%, respectively, and GMCPG-NS structure reduces the leakage power in between 69% and 92%, and wake-up time by 27-46% for different ISCAS85 power gated modules compared to the MOSPG structure. Both multimode PG structures are able to reduce the leakage power as compared to the other PG structures with improvement in the wake-up time by 99%.