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Abstract Analog circuits are essential part of nearly all the IC industry making nearly 15% of the share of its market. The process of analog IC design is known to be time consuming and error prone. According to a statistical data published by Electronic Design Automation EDA weekly on 2005, Analog design takes nearly 40% of the design effort and causes about 50% of the errors found. This is although analog components represent usually only 3% of the area in system-on-chip designs. This thesis presents a new analog layout design tool for placement and routing of circuits, the main scope is to build a complete routing tool but from the research we have proved that placement and routing are totally dependent on each other. For placement tool we developed innovative template algorithm to decrease the solution space in an effective way then an optimization method to choose the best placement using satisfiability modulo theories SMT linear Solver, then the tool start the routing phase in two steps the first to route the main sub-blocks as will be identified through the thesis and the second step by using an enhancement Dijkstra algorithm to find the shortest path and taking into consideration more layout constraints like parasitic, electromigration, Manhattan routing techniques, ..etc. This tool built in a way to consider the most advanced techniques used in today`s industrial products as well today advanced deep nodes to decrease the design cycle and layout iterations. This tool extracts the main sub-blocks types from the schematics then starts processing on each sub-block like current mirrors and differential pairs, to find the best matching pattern that satisfies the block constraints and estimate the needed routing taking the parasitic into consideration, then checking the available space for routing between blocks using a modified Dijkstra Algorithm to find the shortest path between the connected pins, and finally the tool draw the actual routes and placed them in the layout view. |