الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
3D integration has emerged as an effective way to improve the performance of microelectronic devices. Compared with 2D classical schemes, 3D integration has a lot of benefits such as shorter interconnection, heterogeneous integration, and power consumption reduction. In this regard, Through Silicon Vias (TSVs) provide the vertical connection between stacked chips. They minimize the interconnect paths leading to a reduction in parasitic capacitance and resistance and offer small packaging sizes. However, TSV interconnects face some challenges in design and fabrication. Some of these issues are via etching and filling, thermal management, and floor planning.
Due to differences in the coefficient of thermal expansion (CTE) between the bulk and the TSV filling material, stresses are generated in the bulk around the TSV during thermal cycles. These generated stresses may lead to damage or crack of the wafer and interfacial delamination of TSV. Moreover, the mobility of carriers is changed due to the generated stresses. There would be an area around TSV where the transistors and active elements should be put away. This area is called keep out zone (KOZ) where the stresses are very high and affect the reliability of transistor performance.
Tunnel field effect transistor (TFET) is proposed as a good alternative to MOSFET transistors where the current is mainly due to band to band tunneling phenomena instead of thermionic emission as in traditional MOSFETs. TFET has advantages over MOSFET of low leakage current, low power supply, and a better ION/IOFF ratio. However, some challenges face the design of TFET. The ambipolarity and high threshold voltage Vth are the main concern in TFET structures.
In this thesis, a complete study of TSV is presented under different conditions to figure out the best conditions for reliability. The TSV generated stress is analyzed using thermo-mechanical modeling to calibrate the thermal parameters of the materials used. Then a Finite element analysis using Sentaurus TCAD tool is utilized to study TSV’s generated stresses at different conditions including different annealing temperatures, different via diameters, and different liner thicknesses. Then, a KOZ determination is done to find a relation between annealing temperature, via’s radius, and KOZ area. Also, Carbon Nanotubes (CNTs) are used as a filling material instead of Copper to further reduce the generated stresses and decrease the KOZ. A Cu/CNT composite is analyzed also and a ratio of CNT to Cu is presented.
Next, a comprehensive study of TFET is provided as an alternative of MOSFETs including different structures of TFET, non-silicon source TFET, all non-silicon TFET, and a hybrid dielectric gate oxide TFET. Then, a further enhancement to TFET is provided for low power applications. This study is used next to compare bulk MOSFET with bulk TFET under via’s stresses.
Finally, a study of the generated stress’s effects on transistors is presented and analyzed. The influence on the currents and carrier mobility of both TFET and MOSFET are compared for the same channel orientation and same distance.