الفهرس 
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Abstract
A key aspect of digital security is encrypting data by means of encryption systems. Encryption is essential for a wide range of technologies in the daily life. The dedicated hardware devices provide large data processing with high throughput and offer real-time encryption if required. The preferred solution is implementing the encryption algorithms on the Field Programmable Gate Array (FPGA). The FPGA is low-cost, versatile and robust. For encryption systems, in particular, the FPGA is able to be reconfigured for any new security requirements. FPGA is the practical solution for embedded systems and high-speed applications..
This work presents different techniques of implementing the digital hardware circuits for the encryption systems from the basic units to the prototype of the whole sender and receiver hardware circuits. The descriptions of the basic units or the complete encryption system have been supported with the mathematical algorithms, in addition to the architecture of the hardware circuit of the existing and the proposed designs. Some common implementation techniques have been introduced to enhance the performance of digital circuits and the mathematical operators which depend basically on the modular arithmetic. The logic gates, adders, subtractors, multipliers, registers, multiplexers which used in the hardware architecture description are based on the built-in units already exist in FPGAs.
The basic algorithms of modular reduction have been introduced, in addition to its implementations. The algorithms and hardware circuit architectures of modular adder, multiplier, exponentiation, and modular inverse multiplier have been introduced combined with different implementation techniques to decrease the cost of area or increase the speed. The preceding modular units are the basic units for the construction of public-key encryption systems. The descriptions of the various encryption systems focus on the algorithms, the combination of basic modular operation units, and the circuit architecture of the encryption algorithm. Examples of three encryption systems have been described. These are Message Encryption, Key Agreement, and Digital Signature.
The modular multiplier is the main engine of the public-key encryption systems. Five novel designs of modular multiplier based on Montgomery Modular Multiplier (MMM) have been proposed and implemented on FPGAs. The proposed algorithms represent a modification of the radix-2 MMM structure to improve the maximum frequency, area, and efficiency. The new algorithms have the ability to be configured for any arbitrary bit-length of the operands and modulus. The proposed designs have been coded in VHDL, targeting Virtex-6, Virtex-7, and Spartan-6 Xilinx FPGAs platform. The proposed designs have been synthesized by Xilinx ISE 14.4, and simulated by ModelSim SE 2019.2. A comprehensive analysis has been carried out for each proposed design to compare the synthesis results of the implementation with other related designs using the same FPGA, in terms of area, frequency, data throughput, AT/b and efficiency. The comparison shows that the proposed designs offered a significant decrease in area, lower AT/b, while achieving better implementation efficiency on FPGA than the relevant designs. The Digilent Nexys 3 board with Xilinx Spartan-6 FPGA has been targeted as a practical hardware implementation of the proposed design.