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العنوان
Low Power Circuits for High Speed Serial Links Transceivers /
المؤلف
Allam, Muhamed Fouad Abdelazeem Ibrahim.
هيئة الاعداد
باحث / محمد فؤاد عبد العظيم ابراهيم علام
مشرف / سامح عاصم إبراهيم
مناقش / أحمد نادر محي الدين رزق
مناقش / محمد أمين دسوقي
تاريخ النشر
2021.
عدد الصفحات
125 P.:
اللغة
الإنجليزية
الدرجة
ماجستير
التخصص
الهندسة الكهربائية والالكترونية
تاريخ الإجازة
1/1/2021
مكان الإجازة
جامعة عين شمس - كلية الهندسة - قسم هندسة الالكترونيات والاتصالات الكهربية
الفهرس
Only 14 pages are availabe for public view

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from 125

Abstract

s thesis presents a fully linear model of phase-interpolator-based bang bang digital Clock and Data Recovery System (CDR), enabling accurate estimation of jitter tolerance (JTOL) and jitter-transfer (JTRAN). The model is based on linearizing the decimator block in a stochastic sense —independent of the CDR loop dynamics—and deriving JTOL behaviour for digital CDR separately. This thesis also compares most commonly used decimator topologies and their effect on the CDR noise performance. Consequently, it proposes a new decimator topology to decouple the CDR JTOL from JTRAN, enhanc- ing the CDR jitter peformance. The proposed model and the new decimator topology are both verified through MATLAB/Simulink simulation of the CDR, measuring the JTRAN and JTOL of the nonlinear model and comparing it to that of the proposed linear model. The objective of the thesis is driven by the need of accurately modeling the CDR and providing a simple an intuitive explanation for the nonlinear CDR blocks behavior and effect on the jitter performance of the CDR. The thesis also presents a fast-switching phase-interpolator (PI) operating at 5-GHz with superior linearity. The PI is designed for high bandwidth clock and data recovery (CDR) to enable high jitter- tolerance (JTOL) in serial-link applications. It is based on a current-switching topology to enable a high phase-update rate. It also employs an adaptive regenerative amplifier (ARA) to prevent amplitude-dependent delays. This PI consists of cascaded trigono- metric phase-interpolator (TPI) and linear phase-interpolator (LPI) stages together with cross-coupled devices load to immensely enhance its linearity, enabling an 8-bit resolu- tion with an integral nonlinearity (INL) of 0.5 LSB and differential nonlinearity (DNL)
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of 0.15 LSB. The PI is implemented in 65-nm CMOS technology, operating from a 1.2 V supply with a current consumption of 26 mA.