الفهرس 
SCOPE AND CONTRIBUTIONS
2.5D/3D IC PROPOSED PROGRAMMABLE CHECKER FOR CANDIDATE HOT JUNCTION DETECTIONOnly 14 pages are availabe for public view
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Abstract
Many challenges accompany the use of 3D integrated circuits. Some of these challenges are design-related, while others are verification-related. In this dissertation, the focus is on verification issues; more precisely, on advanced layout physical verification tasks such as electrostatic discharge robustness, advanced latch-up design rule checks, and candidate hot junction detection.
The dissertation explains the differences and additional challenges compared to conventional 2D IC verification. It introduces a programmable checker to tackle these verification challenges using automation for complete 3D IC designs. The checker differentiates between external and internal inputs/outputs from the assembly level without using layout markers on the die level. This checker verifies correct, incorrect, and missing ESD protection circuitries for each category of inputs/outputs. Furthermore, the checker inspects total parasitic resistance and performs current density analysis for the relevant interconnect routes through the entire 3D IC design layout to ensure these routes can sustain the ESD event. The checker also verifies external latch-up design rules using a topology-aware analysis, and checks for mixed voltage latch-up design rules using a voltage-aware analysis. Finally, the checker identifies candidate hot junctions, because their existence can cause damage if the voltage rises too high and the current is not sufficiently limited.
This dissertation uses a design to illustrate the different type of checks, explain how to setup required input constraints, share captured results/violations, and demonstrate how to effectively debug results to overcome potential design weaknesses.