الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
Analog-to-digital converter (ADC) is considered the link between the real world, represented by real-time analog signals and the digitized world, represented by digital integrated circuits, microprocessors and microcontrollers. ADCs are the key components in most recent electronic devices especially in software-defined radio (SDR), biomedical devices and low-power electronic devices.
Recent ADC architectures are facing many serious limitations due to CMOS technology scaling. One of these limitations is the degradation of the signal-to-noise ratio (SNR) due to the reduction of the supply voltage. Moreover, the dynamic range of analog input signal is reduced as the threshold voltage is not affected by the continuous scaling of CMOS transistors.
These limitations led to the design of the time-based analog-to-digital converter (T-ADC). In this ADC, the input voltage signal is converted to a delay signal first where the delay is proportional to the input signal value. Following that, this delay signal is converted to a digital code. This allows the processing of the signal to be in the time domain. However, the performance of the Voltage-to-Time Converter (VTC) circuit in the T-ADC is limited by two major drawbacks. These drawbacks are the output delay non-linearity and the limited dynamic range of the input signal.
In this Thesis, two proposed 5 bits voltage-to-time converters are presented for T-ADCs at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These proposed converters exhibit better linearity which is analytically proven in the thesis. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology and the proposed ADCs operate at a clock frequency of 500 MHz.
Thanks to their simple design, the proposed VTC circuits occupy a small area of 26.67 μm2 for the first proposed VTC and 11.16 μm2 for the second proposed VTC, while consuming very small power of 18 μW for the first proposed VTC and 15 μW for the second proposed VTC. The effect of PVT variations on the proposed designs is discussed. In addition, calibration circuits are proposed to overcome the limitations in the VTC circuits’ performance due to these variations. Moreover, Time-to-Digital Converter (TDC) is proposed as the performance of the VTC is limited by the design of the time-to-digital converter (TDC) circuit that follows it. The TDC affects the linearity of the whole ADC and its performance should be investigated. Differential non-linearity (DNL) and integral non-linearity (INL) for the whole ADC are calculated as they are the most important parameters that represent the linearity in the whole ADC.
Since the proposed designs are suitable for applications with limited power budget, such as internet of things (IoT) and wearable devices, the proposed VTC circuits can be applied for low-resolution ADCs for wireless communication receivers in Multiple-Input Multiple-Output (MIMO) systems as the power consumption is a much more important factor than resolution.
Hence, a 3-bit highly linear Time-based Analog-to-Digital Converter (T-ADC) is proposed. This proposed ADC exhibits high linearity, simple design and low power which make it the best solution for the problems that limit the performance of the MIMO systems. The proposed ADC exhibits a maximum linearity error of 0.56 %, a wide input dynamic range of 800 mV and a low power of 2.2 mW. The supply voltage used equals to 1.2 V in industrial hardware-calibrated TSMC 65 nm CMOS technology. The proposed ADC operates at a clock frequency of 4 GHz and a maximum input frequency of 2 GHz.