الفهرس 
English Cover
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Abstract
In this thesis a novel ring amplifier architecture is proposed. This structure is the first of its kind in which it enables the usage of ring amplifier in continuous time applications. The new structure design and design equations is clarified with the help of a design example of second order continuous time modulator. Then, the proposed architecture is used to implement a more complex third order, 1.5 bit quantizer V4 modulator. The modulator is implemented in a 65nm CMOS technology and can achieves a SNDR of 66 dB for a 5 MHz BW input signal while consuming only 1.5 mW from a 0.9 V single supply. Hence, achieving a Figure of Merit (FoM) of 92 fJ/Conv