الفهرس 
Title : Exploring the simulation of dynamic partial reconfiguration for network on chip (NOC)-based FPGA
SummaryOnly 14 pages are availabe for public view
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Abstract
In this thesis, a literature survey of exiting Dynamic Partial Reconfiguration (DPR) techniques forconventional FPGAsis presented. Then, a comparative review ofthese techniques is providedwith respect to reconfiguration time and area. Following that, different network parameters at the NoC-based FPGAs have been analyzed to estimate the impact on DPR performance usinga state-of-art simulator2NoC-DPR3, Finally, a case study is introduced to clarify the DPR performancegap between NoC-based FPGAs and conventional FPGAs