الفهرس | Only 14 pages are availabe for public view |
Abstract A novel reconfigurable hardware design is proposed for implementing different communication chains usingDynamic Partial Reconfiguration (DPR) and results shows an improvement in area and power consumption. This proposed work shows the advantages of using FPGA feature, Dynamic Partial Reconfiguration (DPR), in the implementation of Software Defined Radio (SDR) System that can switch among different communication standards in runtime |