الفهرس 
DLL system analysis
Voltage-controlled delay lineOnly 14 pages are availabe for public view
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Abstract
In the recent years, the delay-locked loop (DLL) is widely used for data synchronization, high-frequency clock generation by frequency multipliers, memory interfaces, and clock deskew applications.
This thesis introduces the design of a wide-range high-speed DLL. Different DLL architectures have been discussed. The top-level system design and the circuit design of each sub-block have been mentioned. Addressing multiple noise source cancellation to achieve low static phase error, a low noise charge pump has been presented. The contribution of this thesis can be summarized as follows:
• Constructing a DLL architecture to achieve wide-range high-speed frequency operation without locking issues and with low noise clock output
• Combining multiple noise source cancellation in CP circuit, introducing a modified charge pump to achieve low static phase error.
• The presented DLL operates at 0.75-5 GHz frequency range and has 8-phases output clocks with 45º phase difference.
• The DLL has been designed in a 22-nm CMOS process. The measured root-mean-square and peak-to-peak jitter are 0.5 ps and 1.83 ps at 5 GHz, respectively. The power dissipation is 14.8 mW for a supply voltage of 0.9 V.