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Abstract
New advances in the fi of digital transmission systems and microelectronic tech- nology have recently led to the discovery of more and more powerful channel coding techniques based on iterative decoding, which achieve performance near to the Shannon limit of channel capacity. This stimulated the rediscovery of the Low-density-parity-check (LDPC) codes. LDPC codes have recently attracted tremendous attention due to their ability to achieve high performance near to the Shannon limit. It is usually decoded with an iterative decoding process to obtain the optimal decoding performance with moder- ate complexity. On the other hand, the larger number of decoding iterations, the less decoding throughput and the longer decoding latency. To achieve a high decoding date rate, a large number of computation units are required for an LDPC decoder, which leads to large chip area and high power consumption. LDPC code gives excellent coding gain and very low error fl or. Compared to other error correcting codes such as Turbo codes,Bose-Chaudhuri-Hocquenghem multiple error correction binary block (BCH)codes and RS codes, LDPC code has many more varieties in code construction, which result in various optimum decoding architectures associated with diff t structures of the parity-check matrix. In this thesis, We present a fi programmable gate array (FPGA) architecture for LDPC decoder for the digital video broadcasting terrestrial two(DVB-T2) system. A layered decoding approach is taken to achieve an appropriate trade-off between hardware complexity and decoding throughput, while simultaneously resolving the mem- ory conflict problem.