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Abstract
With the arrival of chip multiprocessor systems, Network-on-Chip (NoC) has started to form the backbone of communication within a microprocessor chip. However, unfortunately, the performance of NoC is bounded by the limited power and area budgets. Bufferless NoC has emerged as a solution to reduce power and area. Bufferless NoC eliminates the buffers used for routing and/or flow control and handle contention using packet dropping or packet deflection. In this thesis, we focus on enhancing the performance (latency and deflection count) of deflection-based bufferless NoC running latency-sensitive applications. First, we present an analytical study for the traffic in bufferless NoC under the Maximum Flexibility (MaxFlex) selection function with different step sizes. We also provide an experimental study under MaxFlex. Simulation results show that with large values of step size, the latency could be reduced by 97% over using Straight Line selection function. The proposed analysis explains the outperforming experimental results. Then we propose different flit ranking policies that focus on decreasing the deflection count of the flits. Simulation results show that the proposed ranking policies can reduce the latency by up to 58% compared to Oldest First policy. Finally, we consider relaxing the effect of congestion in bufferless NoC under high injection rate. We propose two approaches for congestion prevention. The first considers running applications on NoC with extra nodes. The second considers dividing a certain load into a sequence of lighter loads. Simulation results show that the proposed approaches enhance the latency by up to 61% in addition to operating at higher injections rates