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Abstract
The missing fourth passive circuit element, the memristor, attracted a great attention when HP labs developed the first real memristor device in 2008. The memristor manufacturing is facing various challenges due to the difficulty to control its process variation, as it is fabricated at nano-scale geometry{u2019}s size. Process variation deviate the actual electrical behavior of memristors from the desired values. This deviation reduces the yield especially in the memristor-based memory design. The yield is defined as the number of memristors that exhibit correct writing/reading operation. The process variations sources are line-edge roughness (LER), oxide thickness fluctuation (OTF), and random discrete doping (RDD). In this work, we analyze the impact of the process variations on the electrical properties of both TiO2 thin-film and spintronic memristors. A compact model is proposed to generate a large volume of process variation-aware three-dimensional device structures for Monte-Carlo simulations. Therefore, it is very important to understand and characterize the impact of process variation on memristor performance and yield and attempt to optimize the yield