الفهرس 
INTRODUCTIONOnly 14 pages are availabe for public view
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Abstract
Many important signal processing and communication algo-rithms use multiplication intensive operations and owing to the fact that speed and cost are the most important design criteria, digital signal processing (DSP) engineers have exp-lored speed/cost efficient techniques for computing these operations. Taking into consideration circuit complexity, hardware area, pin limitations, execution speed, and data transfer type, the serial-parallel multiplier is most Buit-able for digital signal processing.
With the advance of VLSI technology, large integration of processing elements which can cooperate with each other to accomplish massive computation tasks, have resulted in higher speed. However, owing to the increasing comlexity and density of VLSI circuits, any failure of a chip may aeriously affect all the operations of the aystem, and hence high computing reliability is required to ensure validity and integrity of computed results specially long computaions in some critical fields such as radar communication and real time image pro¬cessing for robotics control.
This thesis is divided into two main parts. The first part proposes a new architecture for a serial-parallel multiplier called Modified Fast Serial Parallel (MFSP) multiplier that can be used when the chip size is limited for high speed
applications, i.e., the case in which a compromise between the speed, area and hardware overhead is considered. The pro¬posed multiplier uses a 4-bits fast adder stages connected in cascade instead of the second row of parallel ripple carry adder of the fast serial parallel (FSP) multiplier. The vali¬dity of this multiplier is teated by computional comparisons with the CSAS, FSP and NFSP multipliers based on speed and hardware factors for different sizes of multipliers
The second part of the thesis proposes a new fast model of serial parallel multipliers with concurrent error detection (CED) by using REcomputing with Circularly shifted Operands (RECO) technique applied to the MFSP multiplier introduced in the first part. In this proposed model, it was tried to make a compromise between suitable error coverage, small error latency, suitable multiplication speed improvement over that of the CSAS multiplier with RECO technique and low hardware overhead as possible. The error detection capabilty is dis¬cussed, the error performance and fault coverage for multi-pliers of sizes 8 and 16 bits are studied through computer simulation. Speed and hardware comparisons to the CSAS multi-plier are also made.
This thesis consists of six chapters. Chapter one is an introduction and reviews the previous works. Chapter two dis-cusses the digital multiplication techniques and recent mult-ipliers. The proposed MFSP multiplier is introduced and
discussed in chapter three, also chapter three provides com¬parative study of the MFSP multiplier with three recent ser-ial parallel multipliers. Chapter four presents the con¬current error detection using time redundancy techniques and discusses the application of the RECO technique to the CSAS multiplier. In chapter 5, the proposed MFSP with concurrent error detection with RECO technique iB introduced and stud¬ied. The error detection capability of the RECO technique applied to this multiplier is formulated. The error perfor¬mance, fault coverage are studied through computer simultion. The speed and hardware comprisons with the nonredundant CSAS multiplier and the CSAS multiplier with RECO technique are also made.