الفهرس يوجد فقط 14 صفحة متاحة للعرض العام
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المستخلص
The field programmable gate arrays (FPGAs) are widely used in the hardware implementation of many designed circuits. We now introduce new diagnosis procedures, these procedures are based on Chwa-Hakimi model which provides the ability to increase the capability of faults detection. In this thesis, the shifting technique is used in the diagnosis procedures to save the off-chip memory, and the time for loading different configurations The process of test and diagnosis consists of three stages.
1- The first is to test the FPGA and locate the faulty nodes (each node contains many CLBS) inside the FPGA. The FPGA is divided into n nodes, and every two units can test each other. So the diagnostic graph is undirected graph. Then test outcome is either ”pass” if the two nodes are fault- free or ”fail” if at least one of them has an error. Each node should be diagnosed by at least 1(n-2) other nodes.
2- The second is to identify the faulty CLBS inside the faulty nodes that detected in the first procedure. A faulty node is compared with a fault- free one to identify the faulty CLBS inside the faulty node.
3- The third is to identify the faulty elements inside the faulty CLBs. which allows partially using of the defective FPGA resources (fault-tolerance). This procedure is divided into two main stages, one for rows testing and the other for column testing. Every stage consists of a number of steps that are chosen according to the internal construction of the CLB, and aims to testing one or more elements inside it
These procedures have the following advantages.
1- The capability of detecting a large number of faulty nodes.
2- Capability of identifying the faulty CLBS in the chip. 3- The capability of identifying the faulty elements
inside each faulty CLB, which increases the chance of applying the fault-torelent technique.
4- No hardware overhead.
5- These procedures are achieved by a minimum number of test configurations.
6- Less testing time due to the using of a shifting technique (the test time depends on the size of the FPGA and on the number of faulty nodes).
7. The reliability of identifying the faulty nodes, CLBs and parts in each CLB is very high without invalidation in testing or diagnosis analysis.
Once a fault CLBS is detected, information about the location of the faults can be passed back to the compiler so the system can be reconfigured to avoid the fault and run as fault-free one.