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العنوان
Study and Modeling of the Noise and the offset volyages in mosfet vlsi Operational Amplifier’s
الناشر
:Mohamed Abd El Fatah Farid
المؤلف
Farid, Mohamed Abd El-Fatah .
هيئة الاعداد
باحث / محمد عبد الفتاح فريد
مشرف / محمد نبيل صالح
مشرف / عادل عزت الحناوى
مناقش / م.م.ابراهيم
مناقش / م.ن. صالح
الموضوع
amplifiers
تاريخ النشر
, 1989
عدد الصفحات
83p
اللغة
الإنجليزية
الدرجة
ماجستير
التخصص
الهندسة الكهربائية والالكترونية
تاريخ الإجازة
1/1/1989
مكان الإجازة
جامعة عين شمس - كلية الهندسة - الالكترونيات
الفهرس
Only 14 pages are availabe for public view

from 138

from 138

Abstract

In recent years trends towards employing MaS VLSI technology
in manufacturing the high gain op-arnp has been increased.
This can be refered to the following advantages : -
1- Simple construction and better reliability.
2- High MOSFET gate resistance which makes possible to obtain a
very high op-amp input impedance.
3- Low cost.
4- Very negligibly small leakage current.
On the other hand, MOSFET technology is associated with the
following limitations: -
1. The relatively high offset voltages (2 - 20).1V).
2. High drift voltage (2 - 250).1v/oe).
3. Noise voltage levels as high as 250 ).IVpeak are observed.
These drawbacks are related to the fluctuation of the technolo- gical and electrical parameters and to the SI - Si02 interface of
building blocks employed in constructing the analog amplifier. Several
techniques have been used to minimize these drawbacks and consequently
to improve the amplifier performance and increase the gain band width
product; these are : - 1- Employing the E/O MOS and/or 50S technology, to improve the
Si - Sio2 interface properties. Unfortunately, only slight
improvement is gained in this direction.
2- Memorization of the amplifier defects in analog capacitance
and substracting it from that superimposed on the input signal
to be amplifier. In this technique, the stored data must be
frequently refreshed to compensate for the leakage. Also
switching parasitics introduce new interfering signal. The
storage capacitance must belarge compared to the switches
capacitances to decrease as possible these parasitics. This
leads to large surface and consequently to a greater cost
per chip.
3- Topological interdigitation, this technique is used only with
the analog amplifiers imploying large ~05 transistor. Also
it does not perform a perfect offset rejection since parameters
fluctuations are not linear in distance •
Hence we present a new technique, for offset and defects compen-
sation, which is reduces the above mentioned drawbacks. It
is permanent, very simple, and does not need any refreshment. In Chapter [1] we present a survey of the high gain low level
MOSFET amplifiers.
In Chapter [2] we study and model the offset voltages and their
dependance on the temperature, the surface charges, the scalling down
and hot carrier phenomena and the noise voltages which become no
longer negligible.
In Chapter [3] we present a survey of the traditional methods
used to eliminate these defects (memorization and substraction using
a capacitor, topological interdigitation and the geometry reduction).
These techniques are neither eff I cient nor si rnple, We present
afterwards a new technique which is based on the hot carrier injection
into a floating gate. This technique can efficiently compensate for the
offset voltages. This floating gate serves also to shield the gate
electrode from noise resulting from channel and oxide activities. This
technique is simple, very accurate, permanent and economic.
In Chapter [4] we present the experimental results. A very good
agreement has been observed between models and measurements.We finally present our Conclusions and propose new points for
futur research in Chapter [5].